A desired feature in some phase locked loops (PLL) is aligning a clocked output and a divided down (in frequency) version of the clock, e.g., to align two clocks which are integer multiples of each other. In the known art, simple dual latch designs have been utilized, however, these designs do not preserve the 50% duty ratio for odd divide ratios. Moreover, alignment of the clock signals has been difficult due to delay through the clock dividers as the result of temperature, voltage operating range, and processing.
As shown in FIG. 1, a clock signal (Clock A) can be applied to a divider 11, e.g., a 2-8 divider, to produce an output Clock B. Thus, Clock B is derived from a divided down earlier version of Clock A. However, as discussed above, delay through divider 11 can vary, e.g., due to temperature, voltage, processing. A graphical representation of this delay is shown in FIG. 2, in which the rising edge of the output from the divider CLOCK B is delayed from the rising edge of the input to the divider CLOCK A. Further, the delay in the divider may be different depending upon the divide ratio. By way of example, for even divide ratios, the delay may be, e.g., 97 picoseconds, while for odd divide ratios, the delay may be, e.g., 94 picoseconds. As a result, up to a 400 picosecond delay may be achieved over all divide ratios. Moreover, with arrangement shown in FIG. 2, CLOCK B for odd divide ratios does not have a 50% duty cycle.